JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, has announced the publication of JEP184: Guideline for evaluating Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semiconductor (MOS) Devices for Power Electronic Conversion. The publication developed by JEDEC’s JC-70.2 Silicon Carbide Subcommittee, is available for free download from the JEDEC website.
JEP184 provides definitions and procedures for characterizing the threshold voltage instability of SiC-based power electronic conversion semiconductor devices having a gate dielectric region biased to turn devices on and off.
Bias Temperature Instabilities (BTI) involve variations of threshold voltage (VT) and other device parameters such as resistance in the on-state and leakage current in the off-state as a function of the stress time, stress voltage, and stress temperature. The assessment of BTI in SiC MOSFETs is particularly challenging since the measured threshold shift can be composed of different components such as long-term VT drift, transient VT changes, and hysteresis behavior or changes in hysteresis.
This publication provides guidelines for stress procedures being able to distinguish between different shift components and allowing measurement of their stability over time as affected by gate bias and temperature. JEP184 also closely follows the recent JEDEC publication of JEP183: Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs. Together, these two closely related publications provide the industry much-needed guidance on assessing and evaluating BTI variations of VT, as well as accurately measuring the VT of SiC MOSFETs.
“BTI is a frequently requested topic of interest from the automotive and industrial markets adopting SiC power MOSFETs. We believe adding JEP184 to address BTI fills a critical need in this space, and we are grateful to have active participation in JC-70.2 on BTI,” noted Dr. Jeffrey Casady, Wolfspeed Power Die Product Marketing Engineering Manager, Cree, and the chair of the JC-70.2 subcommittee.
“JEDEC’s JC-70 committee is pleased to add JEP184 to its expanding ecosystem of publications. After releasing the first guideline for SiC specific test procedures (VT) in January (JEP183) we are excited to now start the series of reliability related documents. The outcome once again documents the great effort of our international team” said Dr. Peter Friedrichs, Vice President SiC, Infineon Technologies, and the vice-chair of the JC-70.2 subcommittee.
Formed in October 2017 with twenty-three member companies, JC-70 now has over 60 member companies, which underscores industry commitment to the development of universal standards to help advance the adoption of wide bandgap (WBG) power technologies. Global multinational corporations and technology startups from the US, Europe, Middle East, and Asia are working together to bring to the industry a set of standards for reliability, testing, and parametrics of WBG power semiconductors. Committee members include industry leaders in power GaN and SiC semiconductors, as well as users of wide bandgap power devices, and test and measurement equipment suppliers. Technical experts from universities and national labs also provide input. Interested companies worldwide are welcome to join JEDEC to participate in this important standardization effort. The next JC-70 committee meeting will be held on May 18, 2021 on a virtual platform.
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 300 member companies work together in 100+ JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website.