ALD810030SCLI

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ALD810030SCLI Image

The ALD810030SCLI from Advanced Linear Devices is a Quad Supercapacitor Auto Balancing (SAB) MOSFET Array that is designed to provide voltage spike suppression and leakage-current balancing operations in supercapacitors connected in series. It has a drain-source voltage of up to 10.6 V, a gate threshold voltage of 3.00 V, and a drain-source on-resistance of 26000 Mega-Ohms. This MOSFET has a continuous drain current of less than 80 mA. It uses a combination of four MOSFET devices that are connected across each supercapacitor stack to balance the leakage current and prevent over-voltage events.

This MOSFET array is given a precision gate threshold voltage and exhibits complementary opposing current levels resulting in little additional leakage current, thereby balancing each supercapacitor to within its voltage and current limits. It is available in a surface-mount package that measures 3.5 x 9.80 mm and is ideal for series-connected supercapacitor cell leakage balancing, zero-power voltage divider, matched current mirrors, current sources, scaled supercapacitor stacks and arrays, long-term battery backup, and energy harvesting applications.

Product Specifications

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Product Details

  • Part Number
    ALD810030SCLI
  • Manufacturer
    Advanced Linear Devices
  • Description
    Quad Supercapacitor Auto-Balancing MOSFET Array

General

  • Types of MOSFET
    N-Channel Depletion Mode
  • Technology
    Silicon
  • Transistor Polarity
    N-Channel
  • Dimensions
    3.5 x 9.80 mm
  • Number of Channels
    Quad
  • Continous Drain Current
    0.08 A
  • Drain Source Resistance
    26000 MegaOhm
  • Drain Source Breakdown Voltage
    10.6 V
  • Gate Source Threshold Voltage
    3 V
  • Power Dissipation
    0.5 W
  • Temperature operating range
    -40 to 85 degree C
  • Industry
    Commercial, Industrial
  • Package Type
    Surface Mount
  • Package
    16-Pin SOIC
  • Applications
    Series-connected supercapacitor cell leakage balancing, Energy harvesting, Long term backup battery with supercapacitor outputs, Zero-power voltage divider at selected voltages, Matched current mirrors and current sources, Zero-power mode maximum voltage limiter, Scaled supercapacitor stacks and arrays

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